This application claims the priority benefit of Taiwan application serial no. 89121546, filed Oct. 16, 2000.
1. Field of Invention
The present invention relates to a wafer burn-in method. More particularly, the present invention relates to a wafer burn-in method that uses alternate timing.
2. Description of Related Art
In the manufacturing of semiconductor chips, various integrated circuits are formed on a wafer. The wafer is then cut out and sealed to form integrated circuit packages to be sold in the market.
Because each integrated circuit has its own characteristic properties, internal circuitry has to be checked to decide the quality of the chip. Conventionally, testing is conducted after the silicon chip is sealed. To test the package, voltages are applied to various exposed leads and measured. This process is commonly referred to as package burn-in. However, information regarding the quality of the chip is only obtained after packaging. Hence, packaging material and many processing steps are wasted whenever a sub-quality chip is found. To prevent the above problem, wafer burn-in is conducted in the wafer stage where probes are attached to the bonding pads of a wafer to carry out electrical testing. Any problem on a wafer can be found and tagged before packaging.
To develop memory cell stress during wafer burn-in, considerable time is required. Hence, DC timing must be used to prolong bit line conductance. FIG. 1 is a timing diagram showing voltage variation of various input terminals. As shown in FIG. 1, voltage source VCC, word line voltage VW, word line conduct timing WL are at a high potential state. Because of the use of DC timing and the need for stressing the bit-line and the bit-line bar, the state of bit line voltage VBL and lower electrode voltage VEQ can be arranged into four types of combinations.
The effects of each of the four combinations are further explained below using the capacitor of a DRAM as an illustration. FIGS. 2A through 2D show the four combinations of states for the bit-line and the bit-line bar.
First, in the first combination 10 shown in FIG. 1, the bit line voltage VBL and the lower electrode voltage VEQ are at logic level xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 respectively. Hence, in FIG. 2A, since the upper electrode of the capacitor 18 is connected to the bit line voltage VBL, the upper electrode is at a potential level of xe2x80x981xe2x80x99 potential (a high voltage state). On the other hand, since the lower electrode of the capacitor 18 is connected to the lower electrode voltage VEQ, the lower electrode is at a potential level of xe2x80x980xe2x80x99 (a low voltage state). Thus, a stress from the upper electrode to the lower electrode (up/down direction) is created. Similarly, since the upper electrode of the capacitor 20 is connected to the bit line bar voltage VBLB, the upper electrode is at a potential level of xe2x80x980xe2x80x99 (a low voltage state). Since the lower electrode is connected to the lower electrode voltage VEQ, the lower electrode is at a potential of xe2x80x980xe2x80x99 (a low voltage state). Consequently, the capacitor 20 is in an idle state without any stress.
In the second combination 12 shown in FIG. 1, both the bit line voltage VBL and the lower electrode voltage VEQ are at logic level xe2x80x980xe2x80x99. Hence, in FIG. 2B, since the upper electrode of the capacitor 22 is connected to the bit line voltage VBL, the upper electrode is at a potential level of xe2x80x980xe2x80x99 potential (a low voltage state). Since the lower electrode of the capacitor 22 is connected to the lower electrode voltage VEQ, the lower electrode is at a potential level of xe2x80x980xe2x80x99 (a low voltage state). Thus, the capacitor 22 is in an idle state without any stress. Similarly, since the upper electrode of the capacitor 24 is connected to the bit line bar voltage VBLB, the upper electrode is at a potential level of xe2x80x981xe2x80x99 (a high voltage state). Since the lower electrode is connected to the lower electrode voltage VEQ, the lower electrode is at a potential of xe2x80x980xe2x80x99 (a low voltage state). Consequently, a stress from the upper electrode to the lower electrode (up/down direction) is created.
In the third combination 14 shown in FIG. 1, both the bit line voltage VBL and the lower electrode voltage VEQ are at logic level xe2x80x981xe2x80x99. Hence, in FIG. 2C, since the upper electrode of the capacitor 26 is connected to the bit line voltage VBL, the upper electrode is at a potential level of xe2x80x981xe2x80x99 potential (a high voltage state). Since the lower electrode of the capacitor 26 is connected to the lower electrode voltage VEQ, the lower electrode is at a potential level of xe2x80x981xe2x80x99 (a high voltage state). Thus, the capacitor 26 is in an idle state without any stress. Similarly, since the upper electrode of the capacitor 28 is connected to the bit line bar voltage VBLB, the upper electrode is at a potential level of xe2x80x980xe2x80x99 (a low voltage state). Since the lower electrode is connected to the lower electrode voltage VEQ, the lower electrode is at a potential of xe2x80x981xe2x80x99 (a high voltage state). Consequently, a stress from the lower electrode to the upper electrode (down/up direction) is created.
In the fourth combination 16 shown in FIG. 1, the bit line voltage VBL and the lower electrode voltage VEQ are at a logic level xe2x80x980xe2x80x99 and a logic level xe2x80x981xe2x80x99 respectively. Hence, in FIG. 2D, since the upper electrode of the capacitor 30 is connected to the bit line voltage VBL, the upper electrode is at a potential level of xe2x80x980xe2x80x99 potential (a low voltage state). Since the lower electrode of the capacitor 30 is connected to the lower electrode voltage VEQ, the lower electrode is at a potential level of xe2x80x981xe2x80x99 (a high voltage state). Thus, a stress from the lower electrode to the upper electrode (down/up direction) is created. Similarly, since the upper electrode of the capacitor 32 is connected to the bit line bar voltage VBLB, the upper electrode is at a potential level of xe2x80x981xe2x80x99 (a high voltage state). Since the lower electrode is connected to the lower electrode voltage VEQ, the lower electrode is also at a potential of xe2x80x981xe2x80x99 (a high voltage state). Consequently, the capacitor 32 is in an idle state without any stress.
Following from the aforementioned description, if both the bit-line and the bit-line bar are subjected to a stress, idle state occurs half of the time. Ultimately, burn-in test efficiency is cut in half.
Accordingly, one object purpose of the present invention is to provide a wafer burn-in method that uses alternate timing to prevent idling state and increase operating efficiency.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an alternate timing burn-in method suitable for testing a memory unit on a wafer. First, a first bit line voltage clocking signal is generated and sent to one end of the memory unit. A second bit line voltage clocking signal is generated and sent to the other end of the memory unit. The edge of the second bit line voltage clocking signal corresponds to the mid-point of the first bit line voltage clocking signal. The clocking rate of the first bit line voltage clocking signal and the second bit line voltage clocking signal is at the highest frequency of a station. The memory unit can be a capacitor with the first bit line voltage clocking signal sent to the upper electrode of the capacitor while the second bit line voltage clocking signal sent to the lower electrode of the capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.